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Joe Jakubowski

Joe Jakubowski is the Principal Engineer and Performance Architect in the Lenovo Infrastructure Solutions Group Performance Laboratory in Morrisville, NC. Previously, he spent 30 years at IBM. He started his career in the IBM Networking Hardware Division test organization and worked on various token-ring adapters, switches and test tool development projects. For more than 25 years, he has worked in the x86 server performance organization focusing primarily on database, virtualization and new technology performance. His current role includes all aspects of Intel and AMD x86 server architecture and performance. Joe holds Bachelor of Science degrees with Distinction in Electrical Engineering and Engineering Operations from North Carolina State University and a Master of Science degree in Telecommunications from Pace University.

Joe Jakubowski has authored the following 10 documents. Click one of the links below to show just the documents of that type.

Planning / Implementation Documents by Joe Jakubowski

Tuning UEFI Settings for Performance and Energy Efficiency on AMD Processor-Based ThinkSystem Servers
Planning / Implementation, first published 7 Mar 2020, last updated 12 Jan 2023

Balanced Memory Configurations for 2-Socket Servers with 3rd-Gen Intel Xeon Scalable Processors
Planning / Implementation, first published 23 Aug 2021

Balanced Memory Configurations with 2nd Gen and 3rd Gen AMD EPYC Processors
Planning / Implementation, first published 17 Jan 2020, last updated 26 Jun 2021

Tuning UEFI Settings for Performance and Energy Efficiency on Intel Xeon Scalable Processor-Based ThinkSystem Servers
Planning / Implementation, first published 15 Jun 2021

ThinkSystem Hidden UEFI Parameters
Planning / Implementation, first published 15 May 2018, last updated 18 Mar 2020

Balanced Memory Configurations with Second-Generation Intel Xeon Scalable Processors
Planning / Implementation, first published 2 Apr 2019

System x Hidden UEFI Parameters
Planning / Implementation, first published 6 Mar 2017, last updated 15 May 2018

Balanced Memory Configurations with 1st Generation Intel Xeon Scalable Processors
Planning / Implementation, first published 18 Aug 2017, last updated 20 Nov 2017

Maximizing System x and ThinkServer Performance with a Balanced Memory Configuration (withdrawn)
Planning / Implementation, first published 18 Apr 2016, last updated 4 Oct 2017

Lenovo ThinkSystem SD530 Performance Considerations with 12 DIMMs and 16 DIMMs (withdrawn)
Planning / Implementation, first published 11 Jul 2017

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