Jocelyn Wang

Jocelyn Wang is a Hardware Performance Engineer in the Lenovo Data Center Group Performance Laboratory based in Taipei, Taiwan. She is responsible for performance validation of the PCIe bus and network subsystem, including the RDMA/TCP/UDP protocols on Lenovo ThinkSystem servers. Jocelyn holds a Master's Degree in Biomedical Electronics and Bioinformatics from the National Taiwan University in Taiwan.

Jocelyn Wang has authored the following document.

All Documents by Jocelyn Wang

Measuring the Impact of Memory on RDMA, TCP and UDP Network Performance
Planning / Implementation, first published 30 Oct 2019

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